STM32 Timer Frequency: Choosing PSC and ARR Without Guesswork
Why can a PWM output still be at the wrong frequency after you set both PSC and ARR? Usually the problem is an incorrect timer input clock or a missing “+1” in the register math—not a mysterious timer bug.
Start with the timer input clock
This article uses an up-counting, edge-aligned timer time base. The value you need is the clock actually entering the timer (timerClock), in hertz. It may differ from the CPU clock and from the APB bus clock. STM32 families and APB prescaler settings do not all route clocks in the same way, so confirm the effective timer clock in your part’s clock tree and reference manual.
What PSC and ARR control
PSC is the prescaler. A register value of 71 divides the timer input by 72, because the divider is PSC + 1. ARR is the auto-reload value. In an up-counter, the counter visits zero through ARR, so one period contains ARR + 1 counter ticks. CCR is the capture/compare value; with PWM mode 1, edge alignment, and active-high polarity, it sets the compare point and gives the ideal duty calculation below.
counterClock = timerClock / (PSC + 1)
frequency = timerClock / ((PSC + 1) × (ARR + 1))
period = 1 / frequency
duty = CCR / (ARR + 1) × 100%
These equations describe the stated mode, not every STM32 timer mode. Center-aligned counting, down-counting, repetition counters, preload/update timing, dead time, and inverted outputs need device-specific treatment.
Three hand-calculated examples
1) 72 MHz, 1 kHz, 25% duty
Take timerClock = 72,000,000 Hz, PSC = 71, ARR = 999, and CCR = 250.
- Counter clock = 72,000,000 / (71 + 1) = 1,000,000 Hz.
- Period ticks = 999 + 1 = 1,000.
- PWM frequency = 1,000,000 / 1,000 = 1,000 Hz; period = 1 ms.
- Ideal duty = 250 / 1,000 × 100 = 25%.
2) 72 MHz, 100 Hz, 50% duty
With PSC = 719, ARR = 999, and CCR = 500, the counter clock is 72,000,000 / 720 = 100,000 Hz. Dividing by 1,000 period ticks gives 100 Hz, a 10 ms period, and 50% ideal duty.
3) 80 MHz, 1 kHz, 75% duty
With PSC = 79, ARR = 999, and CCR = 750, the counter clock is 80,000,000 / 80 = 1,000,000 Hz. The result is 1,000 Hz, 1 ms, and 75% ideal duty.
| Timer input | PSC | ARR | CCR | Counter clock | PWM frequency | Period | Duty |
|---|---|---|---|---|---|---|---|
| 72 MHz | 71 | 999 | 250 | 1 MHz | 1 kHz | 1 ms | 25% |
| 72 MHz | 719 | 999 | 500 | 100 kHz | 100 Hz | 10 ms | 50% |
| 80 MHz | 79 | 999 | 750 | 1 MHz | 1 kHz | 1 ms | 75% |
Reproduce the calculation
I maintain the STM32 Timer & PWM calculator. It is a theoretical calculation aid, not an oscilloscope and not ST’s configuration tool. Enter 72000000 Hz, select 16-bit, set PSC to 71, ARR to 999, and CCR to 250, then calculate. The expected counter clock is 1 MHz, PWM frequency 1 kHz, period 1 ms, and duty 25%. Comparing each field with the hand calculation is a useful sanity check.
Boundaries that matter in real firmware
Do not substitute a CPU or APB frequency for the effective timer input without checking the clock tree. Do not drop the +1 terms. PSC and ARR determine the period; CCR determines the compare point. The calculator validates integer register ranges for 16-bit and 32-bit selections, rejects an out-of-range CCR, and its target solver reports frequency error while searching valid integer pairs.
The equations assume a continuously running, up-counting, edge-aligned timer. Startup latency, preload and update-event timing, interrupt or DMA scheduling, output polarity, oscillator tolerance, and board-level effects can change what you observe. Center-aligned and other specialized modes are not interchangeable with this formula.
References and disclosure
ST’s AN4776 timer cookbook provides official timer and PWM configuration examples. For STM32F1 devices, see the general-purpose timer sections in RM0008. Always use the reference manual for the exact MCU and clock configuration.
AI assisted with drafting and language editing. The equations and numerical examples were independently recomputed from the model above; no hardware measurement or performance claim is implied.